// ------------------------------------------------------------------------------
// FileName : counter.v
// Function : The counter module does a simple up-count, with asynchronous reset.  
//            It allows the count to be suspended while the clock still is running.
//
// The count is stored in a register, and the assignments are sequential logic, 
// so the nonblocking assignment operator, <=, is used throughout that block.   
// -----------------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-06-28
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// -----------------------------------------------------------------------------

// unit -> module
module counter #(parameter WIDTH = 4)    // default parameter
                (output[WIDTH-1:0] count, 
                 input clk, count_enable, count_reset
                );
  // ------------ internal variables --------------------------
  reg[WIDTH-1:0] count_reg;   // Store the count. Outputs are always registed.
  wire           clock_wire;  // To gate the clock during disable.
 
  //-------------- main code -----------------------------------
  // Keep the count wired to the output:
  assign #1 count = count_reg;
  
  // Don't count while disabled: clock gating
  assign clock_wire = (count_enable==1'b1)? clk : 1'b0;
  
  // Do the counter: sequential circuit, async-reset
  always@(posedge clock_wire, posedge count_reset)
  begin
    if (count_reset==1'b1) 
           count_reg <= 'b0; // Ignore width.
    else count_reg <= count_reg + 1'b1;
  end
  
endmodule // counter
